This contains the scottyspectrumanalyzer yahoo group backup
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All engineers with a digital background (like me) would say make
a daisy chain for the clock lines and have a 2 resistor 680R network to form a 330R(?)
end termination at the last point.
One R to +5V, one R to ground and the middle of them go to
the signal line.
The digital source driver chip at a star point sees a very
low impedance load and if overloaded may not reach the proper logic levels in
Then all the reflections come back a different times or worse
at near the same time. This could overload the star driver clamping limits.
Digital stars are sort of OK for quite short runs under 4”
10cm and low edge speeds, but some RF chips have 300+ MHz digital clock rates
and happily respond many times to unterminated clock lines as they bounce 2-3
This bouncing matters a lot especially to clocked shift
registers, and their data in and out results.
When simple latch data lines are clocked in then you don’t
care about data line termination providing the data to clock set up and hold
times are met.
If in grief put a series R of say 47R in the clock line source
to help slow down the clock edge speed.
A good ground plane helps a lot.
Unfortunately I am still a long way from getting my own MSA working
to help investigate this.
My suggestion is to follow the current instructions from
Scotty and others until someone can do some measurements.
The Down Under coax builder.